In an integrated circuit a current typically flows from an external pin such as a battery pin into a semiconductor device terminal such as a drain of a Field Effect Transistor (FET) via a connection path within a wiring area, e.g. via connecting wires of the interconnect levels electrically coupled by contact vias.
In semiconductor power device applications large currents have to be directed from external pins to semiconductor device terminals via the interconnect levels. To meet the requirements of reliability and power dissipation capability of semiconductor power devices, a need exists for an interconnect level design to meet those requirements.
For these and other reasons there is a need for the present invention.